1. Field of the Invention
The present invention relates to an A/D (analog-to-digital) converter and an A/D conversion method for converting an analog voltage signal into digital data.
2. Description of Related Art
As disclosed in Japanese Patent Application Laid-open No. 5-259907, it is known to convert an analog voltage signal into a digital signal by use of a pulse-phase-difference coding circuit. It is also known to use the pulse-phase-difference coding circuit as a filter for removing high frequency noises included in an input analog voltage signal as disclosed in Japanese Patent Application Laid-open No. 2002-217758.
FIG. 19 shows a structure of such a pulse-phase-difference coding circuit (abbreviated as “PPDC circuit” hereinafter). As shown in this figure, the PPDC circuit 1 includes a pulse-circulating circuit 2, a counter 3, a latch circuit 4, a pulse selector 5, an encoder 6, and a signal processing circuit 7. The pulse selector 5 and the encoder 6 serve as a device for detecting a position of a pulse circulating in the pulse-circulating circuit 2.
The pulse-circulating circuit 2 has a ring delay line constituted by a plurality of inverting gates 2a and a NAND gate 2b connected in the form of a ring, The pulse-circulating circuit 2 begins an oscillation action (pulse signal circulating action) upon receiving a sampling control signal PA outputted from a control circuit 8 at one input terminal of the NAND gate 2b. The counter 3 counts the number of times that the pulse signal circulating in the pulse-circulating circuit 2 has traveled around the ring, and the counted number is latched into the latch circuit 4 as a binary count signal when the control circuit 8 outputs a sampling control signal PB.
The pulse selector 5 generates a position signal indicative of a position of the pulse signal circulating in the pulse-circulating circuit 2. The encoder 6 generates a binary digital signal corresponding to the position signal received from the pulse selector 5. The signal processing circuit 7 combines the binary digital signal received from the latch circuit 4 as higher-order bits and the binary digital signal received from the encoder 6 as lower-order bits into a digital data set D01 representing a measured phase difference between the sampling control signals PA and PB.
Since the measured phase difference (digital data set D01) varies depending on the analog voltage signal vin applied to the NAND gate 2b and the inverting gates 2a, the digital data set D01 represents the value of the analog voltage signal Vin in digital form.
However, converting an analog voltage signal into corresponding digital data by use of such a PPDC circuit 1 involves a problem in that the binary digital data set D01 varies as ambient temperature varies, because the inverting time of each of the NAND gate 2b and the inverting gates 2a is temperature-dependent.
Japanese Patent Application Laid-open No. 5-259907 discloses also an A/D converter free from such a problem. As shown in FIG. 20, this A/D converter is additionally provided with an input selection switch 11, an output selection switch 12, registers 13, 14 and a divider 15, and uses a control circuit 10 instead of the control circuit 8. The control circuit 10 outputs a selection signal SEL to the selection switches 11 and 12.
The selection switch 11 selects alternately one of the analog voltage signal Vin to be converted into digital data and a reference voltage VR in accordance with the selection signal SEL, and outputs it to the PPDC circuit 1 as an analog voltage signal VD1, The PPDC circuit 1 generates alternately a digital data set DVin corresponding to the analog voltage signal vin and a digital data set DR corresponding to the reference voltage VR. The digital data set DVin and the digital data set DR are sent to the register 13 and the register 14, respectively, through the output selection switch 12. The divider 15 outputs a digital data set D02 representing the value of Dvin/DR as a result of the analog-to-digital conversion.
In this structure explained above, even when the inverting times of the NAND gate 2b and the inverting gates 2a vary due to ambient temperature variation and accordingly the data set DVin representing the voltage signal Vin varies, the output data set D02 of the divider 15 is unaffected by this variation, because the data set DR representing the reference voltage VR also varies in the same proportion so as to set off the variation of the data set DVin. With this structure, it is possible to convert the input analog voltage signal Vin into digital data with little influence of ambient temperature variation.
However, there arises a problem in a case where the reference voltage VR is generated by dividing down a power supply voltage of the A/D converter, and the analog input voltage Vin is applied to the PPDC circuit 1 through an amplifier which uses the reference voltage VR as a potential base thereof. In this case, if the power supply voltage varies, the reference voltage VR varies accordingly. If the level of the reference voltage VR when the input selection switch 11 selects the reference Voltage VR is different from that when the input selection switch 11 selects the analog voltage signal Vin, the analog-to digital conversion results of the A/D converter do not show correct values.
In addition, the prior art A/D converters shown in FIG. 19 and FIG. 20 have another problem explained below.
In the structure shown in FIG. 19 or 20, a period of time between a moment at which the sampling control signal PA is outputted from the control circuit 8 (or 10) and a moment at which the sampling control signal PB is outputted from the control circuit 8 (or 10) defines a sampling time (A/D conversion time) Tc, The resolution of the A/D conversion depends on the sampling time Tc. For example, if the sampling time Tc is doubled, a voltage step corresponding to one bit step is reduced by half, and the resolution is therefore enhanced. For another example, if the sampling time Tc is reduced to 1/10, the resolution is reduced to 1/10. More specifically, in a case where the A/D conversion resolution is 16 bits when the sampling time Tc is 10 μs, if the sampling time Tc is reduced to 1 μs, the A/D conversion resolution is reduced to 13 bits as seen from the graph of FIG. 21.
There is growing need for a knock sensor capable of converting, at high speed and high resolution, weak voltage signals less than 1 mV into digital signals in order to improve knock control of automobile engines. However, the prior art A/D converters as disclosed in Japanese Patent Application Laid-open No. 5-259907 cannot address such a need for the reasons described above.